Current sensing in a disk-drive spindle motor

ABSTRACT

One embodiment of the invention includes a disk-drive spindle motor power regulator system. The system includes a switching system comprising at least one power transistor for each of a plurality of phases of a disk-drive spindle motor. The system also includes a switching controller configured to generate a plurality of switching signals configured to control the at least one power transistor for each of the plurality of phases of the disk-drive spindle motor. The system further includes a current monitor configured to measure a magnitude of an individual phase current through at least one of the plurality of phases of the disk-drive spindle motor.

TECHNICAL FIELD

This invention relates to electronic circuits, and more specifically tocurrent sensing in a disk-drive spindle motor.

BACKGROUND

There is an ever increasing demand for power conversion and regulationcircuitry to operate with increased efficiency and reduced power toaccommodate the continuous reduction in size of electronic devices.Switching regulators have been implemented as an efficient mechanism forproviding a regulated output in power supplies. One such of regulator isknown as a switching regulator or switching power supply, which controlsthe flow of power to a load by controlling the on and off duty-cycle ofone or more switches coupled to the load. Many different classes ofswitching regulators exist today.

Switching regulators can be implemented in any of a variety ofapplications. One such application is in a control system for disk-drivespindle motors. It is sometimes desirable to be able to monitor amagnitude of current that flows through the switches of a switchingregulator for a disk-drive spindle motor, such as to control arotational speed of the disk-drive spindle motor. Some spindle motorpower regulator integrated circuits (ICs) may incorporate additionalinput/output (I/O) pins to accommodate an external sense resistor and/orassociated sensing circuitry. Such methods thus can be subject toadditional cost and/or space to incorporate the additional I/O pins andthe associated circuitry. In addition, typical current sensing schemesfor spindle motor power regulators may incorporate a sense resistor thatinterconnects all of the low-side power transistors with ground or acommon low voltage rail, such that the current that is sensed is anaggregate current of each of the phases of the spindle motor.

SUMMARY

One embodiment of the invention includes a disk-drive spindle motorpower regulator system. The system includes a switching systemcomprising at least one power transistor for each of a plurality ofphases of a disk-drive spindle motor. The system also includes aswitching controller configured to generate a plurality of switchingsignals configured to control the at least one power transistor for eachof the plurality of phases of the disk-drive spindle motor. The systemfurther includes a current monitor configured to measure a magnitude ofan individual phase current through at least one of the plurality ofphases of the disk-drive spindle motor.

Another embodiment of the invention includes a method for measuring anindividual phase current through at least one of a plurality of phasesof a disk-drive spindle motor. The method includes generating aplurality of switching signals that control at least one powertransistor for each of the plurality of phases of the disk-drive spindlemotor and identifying which of at least one of the plurality of phasesthrough which the respective individual phase current is to be measuredbased on the plurality of switching signals. The method also includesswitching a plurality of reference currents corresponding to therespective individual phase current to a respective current sense systemand measuring the magnitude of the respective individual phase currentof the at least one of the plurality of phases based on the plurality ofreference currents. The method further includes calculating a magnitudeof one or more remaining phase currents based on the magnitude of therespective individual phase current.

Another embodiment of the invention includes a disk-drive spindle motorpower regulator system. The system includes means for generating aplurality of switching signals associated with each of a first phase, asecond phase, and a third phase, respectively, of the disk-drive spindlemotor. The system also includes means for generating a first phasecurrent, a second phase current, and a third phase current through thefirst, second, and third phases respectively, of the disk-drive spindlemotor in response to the plurality of switching signals. The systemfurther includes means for measuring a magnitude of two of the first,second, and third phase currents and means for calculating a magnitudeof a remaining one of the first, second, and third phase currents basedon the measured magnitude of the two of the first, second, and thirdphase currents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a spindle motor power regulator systemin accordance with an aspect of the invention.

FIG. 2 illustrates another example of a spindle motor power regulatorsystem in accordance with an aspect of the invention.

FIG. 3 illustrates an example of a current-sense system in accordancewith an aspect of the invention.

FIG. 4 illustrates an example of a high-side current-sense system inaccordance with an aspect of the invention.

FIG. 5 illustrates an example of a phase switch and operationalamplifier (OP-AMP) arrangement in accordance with an aspect of theinvention.

FIG. 6 illustrates an example of a phase switch and OP-AMP system inaccordance with an aspect of the invention.

FIG. 7 illustrates an example of a low-side current-sense system inaccordance with an aspect of the invention.

FIG. 8 illustrates an example of a method for determining individualphase currents of a disk-drive spindle motor in accordance with anaspect of the invention.

DETAILED DESCRIPTION

The invention relates to electronic circuits, and more specifically tocurrent sensing in a disk-drive spindle motor. As an example, thedisk-drive spindle motor can be a permanent magnet three-phasesynchronous DC motor with a center tap of windings that is floating orotherwise unconnected from a low-voltage power rail (e.g., ground). Adisk-drive spindle motor power regulator system includes a switchingcontroller that provides switching signals to a switching system. Theswitching system can include a set of one or more power transistors foreach phase of the disk-drive spindle motor. Therefore, the switchingcontroller can define a commutation state or cycle for the spindle motorthrough each set of switching signals to each of the respective sets ofone or more power transistors to control the rotation of the spindlemotor.

As an example, during each commutation cycle, two sets of switchingsignals corresponding to two of the phases of the spindle motor arepulse-width modulated (PWM) at a fixed PWM frequency. A PWM duty-cyclecan be different for the sets switching signals, with one set of theswitching signals having a greater duty-cycle than the other. The PWMduty-cycle can change for each of the two sets of the switching signalsfrom one PWM period to another, but the relationship between theduty-cycles between the two sets of the switching signals can remain thesame during the commutation cycle. Specifically, one of the sets ofswitching signals can have a PWM duty-cycle that is always greater thanthe other during the commutation cycle, and thus has a greatestduty-cycle in each PWM period of the commutation cycle. The third set ofswitching signals is provided to pull down the respective phase of thespindle motor to the ground during the commutation cycle, such that thethird set of switching signals does not have a PWM duty-cycle. The setsof the switching signals thus control three separate phases of thespindle motor during each commutation cycle.

As described herein, the three phases of the spindle motor are the CAPphase, the SLOPE phase, and the GROUND phase. The respective phases ofthe spindle motor thus conduct a CAP phase current, a SLOPE phasecurrent, and a GROUND phase current, respectively. The CAP phase and theSLOPE phase are each controlled by sets of the switching signals havinga PWM duty-cycle. The PWM duty-cycle of the switching signals thatcontrol the CAP phase is greater than the set of switching signals thatcontrol the SLOPE phase. Thus, the CAP phase current is substantiallyconstantly sourced to the spindle motor during the commutation cycle.The SLOPE phase current, however, changes direction during thecommutation cycle. Thus, the SLOPE phase current is not constantlysourced to the spindle motor during the commutation cycle, but insteadis sunk from the spindle motor during at least a portion of thecommutation cycle. The switching signals that control the GROUND phasedo not have a PWM duty-cycle. Thus, the GROUND phase current issubstantially constantly sunk from the spindle motor during thecommutation phase. The phases change from one commutation cycle to thenext, such as to control the speed and torque of the spindle motor.Thus, the rotation and speed control of the spindle motor can beachieved by combining the proper different commutation states insequence.

The power regulator system can also include a current monitor that isconfigured to measure a magnitude of an individual current flow throughone or more of the phases of the spindle motor during each PWM cycle.The switching controller can identify which of the switching signalscorrespond to control of the associated phases of the spindle motor.Thus, the current monitor can measure the magnitude of the CAP phasecurrent that is substantially constantly sourced to a first phase of thespindle motor during the commutation cycle. The current monitor can alsomeasure the magnitude of the GROUND phase current that is substantiallyconstantly sunk from a second phase of the spindle motor to thelow-voltage power rail during the commutation cycle. The SLOPE phasecurrent can be either a sourcing current or a sinking current, and thecorresponding set of switching signals can have a duty-cycle that isvery small. Therefore, the current monitor may not measure the SLOPEphase current.

The current monitor can include a current sense system for each of thephase currents that are to be measured (i.e., a high-side current sensesystem and a low-side current sense system). The current sense systemscan each include one or more current sensing transistors, such aslaterally-diffused metal-oxide semiconductor field-effect transistors(LDMOSFETs), that are configured to conduct a respective one or morereference currents in response to a control signal that controls thepower transistor. The reference currents can be provided to anoperational amplifier (OP-AMP) that is configured to generate a sensecurrent that is substantially proportional to (i.e., highly linear withrespect to) the output current. As an example, the current sense systemcan include sets of phase switches that direct the reference currentscorresponding to the respective phase to the OP-AMP for measurement, andthe OP-AMP can include a current control circuit that is configured togenerate a sense voltage that is proportional to a magnitude of therespective phase current.

The current monitor can also include an analog-to-digital converter(ADC) that is configured to convert the sense voltage corresponding toeach of the respective measured phase currents to a digital value. Thedigital sense voltages can thus be provided to a processor which cancalculate a delivered power to the disk-drive spindle motor, and thusthe speed of the disk-drive spindle motor. As an example, the currentmonitor can calculate a magnitude of the SLOPE phase current of thespindle motor based on the calculated magnitudes of the CAP and GROUNDphase currents. The phase current magnitude information can thus beimplemented by the processor to control and/or adjust the rotationalspeed and torque of the spindle motor, such as to control the spindlemotor to rotate silently at a substantially constant speed.

FIG. 1 illustrates an example of a spindle motor power regulator system10 in accordance with an aspect of the invention. The spindle motorpower regulator system 10 can be implemented to control the rotationalmotion of a spindle motor 12. As an example, the spindle motor 12 can bea three-phase synchronous DC motor with a center tap of windings that isfloating or otherwise unconnected from a low-voltage power rail (e.g.,ground). The spindle motor 12 can be implemented in any of a variety ofdisk-drive systems. For example, the spindle motor 12 can be implementedin a magnetic disk-drive system such as a hard-disk-drive (HDD) or aperipheral disk-drive, or can be implemented in an optical disk-drivesystem, such as a compact disc (CD) drive, or a digital video disc (DVD)drive. In addition, the spindle motor power regulator system 10 can beimplemented on or as a portion of an integrated circuit (IC).

The spindle motor power regulator system 10 includes a switchingcontroller 14 that is configured to generate a plurality of switchingsignals SW. The switching signals SW are provided to a switching system16 that is configured to control the flow of a set of phase currentsthrough the respective phases of the spindle motor 12. In the example ofFIG. 1, the set of phase currents are demonstrated as a current I_(PH).The switching system 16 includes power transistors 18 that areresponsive to the switching signals SW.

As an example, the switching signals SW can include a high-sideswitching signal and a low-side switching signal for each phase of thespindle motor 12. For example, the switching controller 14 can include aset of drivers for each of the phases of the spindle motor that generatethe respective sets of the switching signals SW in response to one ormore logic signals, such as to substantially mitigate a shoot-throughcurrent through the power transistors 18. As an example, the powertransistors 18 can be LDMOSFETs (hereinafter “FETs”), and can include ahigh-side transistor and a low-side transistor for each of therespective phases of the spindle motor 12. The high-side and low-sideswitching signals of the plurality of switching signals SW can eachinclude one or more digital and/or analog signals corresponding toactivation and/or status of the power transistors 18. Therefore, in theexample of FIG. 1, a portion of the switching signals SW can bepulse-width modulated (PWM) digital signals that can each be separatelyasserted and de-asserted by the switching controller 14 in a givencommutation cycle. For example, two of the sets of the switching signalsSW can have a defined duty-cycle corresponding to control of a CAP phaseand a SLOPE phase, respectively, of the spindle motor 12 and a third setof the switching signals can have no PWM duty-cycle, thus controlling aGROUND phase of the spindle motor 12. Accordingly, the power transistors18 of the switching system 16 are activated and deactivated based on apredetermined PWM scheme to rotate the spindle motor 12 based oncommutation in response to the magnetic field energy generated by theinductive load of the phases.

The spindle motor power regulator system 10 also includes a currentmonitor 20 that is configured to measure the magnitude of at least oneof the individual phase currents I_(PH) that flow through the spindlemotor 12 during each PWM cycle. As an example, the current monitor 20can be configured to measure a magnitude of the CAP phase current andthe GROUND phase current. Specifically, the current monitor 20 can beconfigured to measure a magnitude of the phase current that results froma PWM duty-cycle and is substantially constantly sourced to therespective one of the phases of the spindle motor 12 during thecommutation cycle. The current monitor 20 can also be configured tomeasure a magnitude of the phase current that results from no PWMduty-cycle and thus has a substantially constant flow through therespective one of the phases to a low-voltage power rail (e.g., ground).

In the example of FIG. 1, the switching controller 14 is configured togenerate phase control signals PH that are indicative of which of thephase currents flowing through the spindle motor 12 are to be measured.As an example, in a commutation cycle, the switching controller 14generates two sets of the switching signals SW as having a PWMduty-cycle for controlling the CAP phase current and the SLOPE phasecurrent via the switching system 16. The set of the switching signals SWcontrolling the CAP phase can have a significantly greater PWMduty-cycle in each PWM period of the commutation cycle than theswitching signals controlling the SLOPE phase. The switching controller14 also generates a set of the switching signals SW that is a non-PWMsignal for controlling the GROUND phase current via the switching system16. Therefore, phase control signals PH are provided to the currentmonitor 20 to identify which of the sets of phase currents I_(PH)corresponds to the CAP phase current and which of the sets of phasecurrents I_(PH) corresponds to the GROUND phase current based on themanner in which the switching signals SW are provided to the switchingsystem 16.

The current monitor 20 includes one or more current sense systems 22that are configured to measure the respective phase currents. As anexample, the current sense system(s) 22 can switch reference currentscorresponding to the CAP and GROUND phases, as identified by the phasecontrol signals PH, to an OP-AMP for measurement of the magnitude of therespective phase currents. In addition, the current monitor 20 cancalculate the magnitude of the remaining phase current (i.e., the SLOPEphase current) of the spindle motor 12 to ascertain commutation speedand torque information associated with the spindle motor 12. The currentmonitor 20 can thus generate a feedback control signal FDBK thatcorresponds to commutation speed control of the spindle motor 12. In theexample of FIG. 1, the feedback control signal FDBK is thus provided tothe switching controller 14, such that the pulse-width modulation of theswitching signals SW can be adjusted to appropriately control thecommutation speed and torque of the spindle motor 12, such that thespindle motor can spin silently at a substantially constant speed.

FIG. 2 illustrates another example of a spindle motor power regulatorsystem 50 in accordance with an aspect of the invention. The spindlemotor power regulator system 50 can be implemented to control therotational motion of a three-phase synchronous DC spindle motor (notshown). In the description herein, the three phases of the spindle motorare described as “A”, “B”, and “C”. In addition, as described herein,“X” corresponds to a respective one of the phases A, B, or C of thespindle motor, such as can be applicable to any one or a respective oneof the phases A, B, or C. Similar to as described above in the exampleof FIG. 1, the spindle motor can be implemented in an HDD or aperipheral disk-drive. The spindle motor power regulator system 50 canbe implemented on or as a portion of an IC.

The spindle motor power regulator system 50 includes a switchingcontroller 52 that is configured to generate a set of switching signalsfor each of the three-phases of the spindle motor. In the example ofFIG. 2, the switching signals are demonstrated as SW_A corresponding tocontrol of the first phase of the spindle motor, SW_B corresponding tocontrol of the second phase of the spindle motor, and SW_C correspondingto control of the third phase of the spindle motor. The switchingsignals SW_A, SW_B, and SW_C are provided to a switching system 54. Inthe example of FIG. 2, the switching system 54 includes first phase(i.e., “PHASE A”) power transistors 56, second phase (i.e., “PHASE B”)power transistors 58, and third phase power transistors 60 (i.e., “PHASEC”). The first, second, and third phase power transistors 56, 58, and 60are configured to control the flow of a phase current I_(PH) _(—) _(A),a phase current I_(PH) _(—) _(B), and a phase current I_(PH) _(—) _(C)through the respective phases of the spindle motor.

As an example, each set of the switching signals SW_A, SW_B, and SW_Ccan include a high-side switching signal that controls a high-sidetransistor and a low-side switching signal that controls a low-sidetransistor of the respective first, second, and third phase powertransistors 56, 58, and 60. The high-side and low-side switching signalof each set of the switching signals SW_A, SW_B, and SW_C can includeone or more digital and/or analog signals corresponding to activationand/or status of the power transistors 56, 58, and 60. As anotherexample, the switching signals SW_A, SW_B, and SW_C can each includesignals that mutually exclusively activate/deactivate the high-side andlow-side transistors of each of the respective first, second, and thirdphase power transistors 56, 58, and 60, such as to substantiallymitigate a shoot-through current through the respective high-side andlow-side transistors of each phase of the spindle motor. As an example,the first, second, and third phase power transistors 56, 58, and 60 canbe configured as FETs. The respective high-side and low-side transistorscan thus couple the respective phases of the spindle motor to one of ahigh-voltage power rail 62, demonstrated as having a voltage V_(EXT)that can be a power voltage provided to the IC that houses the spindlemotor power regulator system 50, and a low-voltage power 64,demonstrated as ground. Therefore, in the example of FIG. 2, the sets ofswitching signals SW_A, SW_B, and SW_C can be PWM digital signals thatcan each be separately asserted and de-asserted by the switchingcontroller 52 in a commutation cycle. Accordingly, the first, second,and third phase power transistors 56, 58, and 60 of the switching system54 are activated and deactivated based on a predetermined PWM scheme torotate the spindle motor.

As an example, the switching controller can switch between commutationcycles, such as based on a desired rotation speed of the spindle motor.Each of the commutation cycles can be defined as two of the sets of theswitching signals SW_A, SW_B, and SW_C having the same PWM frequency,with one of the two sets having a higher duty-cycle in each PWM periodof the commutation cycle and the other of the two sets having asignificantly lower duty-cycle in each PWM period of the commutationcycle. The remaining one of the sets of the switching signals SW_A,SW_B, and SW_C can have no PWM duty-cycle. As described herein, havingno PWM duty-cycle is defined as a low-side transistor of the respectiveone of the first, second, and third phase power transistors 56, 58, and60 being activated throughout the entirety of the commutation cycle,such that the respective phase is grounded throughout the entirety ofthe commutation cycle.

The spindle motor power regulator system 50 includes a current monitor66 that is configured to determine the magnitudes of the phase currentsI_(PH) _(—) _(A, I) _(PH) _(—) _(B, and I) _(PH) _(—) _(C) that flowthrough the spindle motor for each PWM cycle. The current monitor 66includes a high-side current-sense system 68 and a low-sidecurrent-sense system 70. The high-side current sense system 68 isconfigured to measure a magnitude of a phase current (i.e., the CAPphase current) that is substantially constantly sourced to therespective phase of the spindle motor in a commutation cycle. As anexample, the CAP phase current can identified as being the one of thephase-currents I_(PH) _(—) _(A, I) _(PH) _(—) _(B), and I_(PH) _(—) _(C)resulting from the corresponding one of the sets of the switchingsignals SW_A, SW_B, and SW_C having the highest PWM duty-cycle in eachPWM period of the commutation cycle. The low-side current sense system70 is configured to measure a magnitude of a phase current (i.e., theGROUND phase current) that is substantially constantly sunk from therespective one of the phases to the low-voltage power rail 64 in thecommutation cycle. As an example, the low-side sinking phase current canbe the one of the phase-currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), andI_(PH) _(—) _(C) resulting from the corresponding one of the sets of theswitching signals SW_A, SW_B, and SW_C having no PWM duty-cycle.

Each of the high-side and low-side current sense systems 68 and 70include a set of sense FETs 72, a set of phase switches 74, and anoperational amplifier (OP-AMP) 76. As an example, for each of thehigh-side and low-side current sense systems 68 and 70, the set of senseFETs 72 can include a pair of matched FETs for each high-side andlow-side transistor of the first, second, and third phase powertransistors 56, 58, and 60, respectively. The pairs of matched FETs canbe configured, respectively, as LDMOSFETs that conduct a first referencecurrent from a phase node associated with the respective powertransistors 56, 58, and 60 and a second reference current from therespective one of the power rails 62 and 64 in response to therespective switching signals SW_X. As an example, each of the FETs inthe sense FETs 72 can have a gate area that is smaller than therespective power transistors in the first, second, and third phase powertransistors 56, 58, and 60.

The phase switches 74 can be configured to switch the reference currentsof the corresponding set of the sense FETs 72 to the OP-AMP 76 formeasurement. Specifically, as described above, the high-side currentsense system 68 is configured to measure the magnitude of the high-sidesourcing phase current, and the low-side current sense system 70 isconfigured to measure the magnitude of the low-side sinking phasecurrent. The switching controller 52 identifies which of the phasecurrents I_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C) is thehigh-side sourcing phase current that is to be measured and which of thephase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C)is the low-side sinking phase current that is to be measured.Specifically, the switching controller 52 generates phase controlsignals HS_PH and LS_PH that are provided to the phase switches 74 ofthe high-side and low-side current sense systems 68 and 70,respectively. The phase control signals HS_PH thus identifies which ofthe phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—)_(C) is the high-side sourcing phase current that controls the CAP phasecurrent and the phase control signals LS_PH thus identifies which of thephase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C)is the low-side sinking phase current that controls the GROUND phase.Therefore, the phase switches 74 can switch the corresponding referencecurrents provided from the sense FETs 72 corresponding to the high-sidesourcing phase current and the low-side sinking phase current to therespective OP-AMPs 76 in response to the phase control signals HS_PH andLS_PH.

The OP-AMPs 76 are configured to measure the magnitudes of the high-sidesourcing phase current and the low-side sinking phase current,respectively. Specifically, the OP-AMPs 76 can generate respective sensevoltages V_(SNS) _(—) _(HS) and V_(SNS) _(—) _(LS) that have magnitudesthat are proportional to (i.e., highly linear with respect to) thehigh-side sourcing phase current and the low-side sinking phase current,respectively, in response to the reference currents that are providedfrom the sense FETs 72 via the phase switches 74. The sense voltagesV_(SNS) _(—) _(HS) and V_(SNS) _(—) _(LS) are each provided to ananalog-to-digital converter (ADC) 78 that is configured to sample andconvert the sense voltages V_(SNS) _(—) _(HS) and V_(SNS) _(—) _(LS) torespective digital values. As an example, the ADC 78 can sample one ormore times during each PWM cycle depending on speed and torque controlrequirements for the spindle motor. The ADC 78 thus generates a digitalsignal DIG_CURR that is indicative of the magnitudes of the sensevoltages V_(SNS) _(—) _(HS) and V_(SNS) _(—) _(LS).

The digital signal DIG_CURR is provided to a processor 80 that can beconfigured to calculate magnitudes of each of the first, second, andthird phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—)_(C). As an example, the processor 80 can be configured to calculate themeasured magnitudes of the CAP phase current and the GROUND phasecurrent by implementing previous calibrated gains and offsets stored inthe processor 80 and assuming a linear relationship from an ADC outputvalue to a measured phase current. In addition, the processor 80 can beconfigured to calculate the magnitude of the remaining one of the first,second, and third phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), andI_(PH) _(—) _(C) (i.e., the SLOPE phase current) in response to thecalculated magnitudes of the high-side sourcing phase current and thelow-side sinking phase currents.

As a result, because the magnitudes of the phase currents I_(PH) _(—)_(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C) are directly related to thecommutation speed and torque of the spindle motor, the processor 80 canbe configured to modify/control the commutation speed and torque of thespindle motor. In the example of FIG. 2, the processor 80 isdemonstrated as generating a feedback control signal FDBK that isprovided to the switching controller 52. Therefore, the switchingcontroller 52 can adjust the pulse-width modulation scheme of theswitching signals SW_A, SW_B, and SW_C in response to the feedbackcontrol signal FDBK. As an example, the feedback control signal FDBK canprovide information as to how the pulse-width modulation of theswitching signals SW_A, SW_B, and SW_C should be adjusted, or canprovide information as to what the pulse-width modulation of theswitching signals SW_A, SW_B, and SW_C should be to compensate for errorin the commutation speed and torque of the spindle motor, such that thespindle motor can spin silently at a substantially constant speed.

It is to be understood that the spindle motor power regulator system 50is not limited to the example of FIG. 2. As an example, one or more ofthe system components demonstrated in the example of FIG. 2 can beconfigured as part of or separately from other demonstrated systemcomponents. For example, the processor 80 can be incorporated into theswitching controller 52, such that the ADC 78 provides the signalDIG_CURR directly to the switching controller 52. In addition, asdemonstrated in greater detail below, additional signal interactionbetween the system components may be omitted from the example of FIG. 2.Thus, the spindle motor power regulator system 50 can be configured inany of a variety of ways.

FIG. 3 illustrates an example of a current-sense system 100 inaccordance with an aspect of the invention. The example of FIG. 3 alsodemonstrates the switching system 54, including the first, second, andthird phase power transistors 56, 58, and 60. The current sense system100 can thus correspond to one of the high-side current sense system 68or the low-side current sense system 70 in the example of FIG. 2.Specifically, the current sense system 100 demonstrated in the exampleof FIG. 3 can be one of the high-side current sense system 68 and thelow-side current sense system 70, such that another current sense systemthat is configured similar to the current sense system 100 can likewisebe coupled with the switching system 54. Therefore, reference is to bemade to the example of FIG. 2 in the following description of theexample of FIG. 3.

In the example of FIG. 3, the first, second, and third phase powertransistors 56, 58, and 60 are demonstrated as FETs. Specifically, thefirst phase power transistors 56 include a high-side power FET HS_A anda low-side power FET LS_A, the second phase power transistors 58 includea high-side power FET HS_B and a low-side power FET LS_B, and the thirdphase power transistors 60 include a high-side power FET HS_C and alow-side power FET LS_C. Therefore, the first, second, and third phasepower transistors 56, 58, and 60 are responsive to the switching signalsSW_A, SW_B, and SW_C, respectively (not shown in the example of FIG. 3),to generate the respective phase currents I_(PH) _(—) _(A), I_(PH) _(—)_(B), and I_(PH) _(—) _(C) by coupling the respective the phases of thespindle motor to either the high-voltage rail 62 (i.e., the voltageV_(EXT)) or the low-voltage rail 64 (i.e., ground).

The current sense system 100 includes a first set of sense FETs 102, asecond set of sense FETs 104, and a third set of sense FETs 106corresponding, respectively, to each of the phases of the spindle motor.In the example of FIG. 3, the phase current I_(PH) _(—) _(A) isdemonstrated as being provided to the first set of sense FETs 102, thephase current I_(PH) _(—) _(B) is demonstrated as being provided to thesecond set of sense FETs 104, and the phase current I_(PH) _(—) _(C) isdemonstrated as being provided to the third set of sense FETs 106. It isto be understood that only a portion of each of the phase currentsI_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C) may be providedto each of the respective sets of sense FETs 102, 104, and 106, asopposed to the entirety of the phase currents I_(PH) _(—) _(A), I_(PH)_(—) _(B), and I_(PH) _(—) _(C).

Each of the sets of sense FETs 102, 104, and 106 can include a pair ofmatched FETs for each of the high-side power FETs HS_A, HS_B, and HS_C,respectively, for the current sense system 100 being configured as thehigh-side current sense system 54. Alternatively, each of the sets ofsense FETs 102, 104, and 106 can include a pair of matched FETs for eachof the low-side power FETs LS_A, LS_B, and LS_C, respectively, for thecurrent sense system 100 being configured as the low-side current sensesystem 70. The pairs of matched FETs can be configured, respectively, toconduct a first reference current from a phase node associated with therespective power FETs 56, 58, and 60 and a second reference current fromthe respective one of the power rails 62 and 64 in response to therespective switching signals SW_X. As an example, each of the FETs inthe respective sets of sense FETs 102, 104, and 106 can have a gate areathat is smaller than the respective high-side or low-side power FETs inthe first, second, and third phase power FETs 56, 58, and 60.

Coupled to the sets of sense FETs 102, 104, and 106 are respective setsof phase switches 108, 110, and 112. The sets of phase switches 108,110, and 112 are configured to switch the first and second referencecurrents from one of the sets of sense FETs 102, 104, and 106, as wellas one or more additional reference currents, such as a third referencecurrent that is also conducted from the respective phase node associatedwith one of the sets of sense FETs 102, 104, and 106 to the OP-AMP 76.In the example of FIG. 3, the reference currents that are provided tothe OP-AMP 76 are demonstrated as currents I_(REF). The switching of thecurrents I_(REF) to the OP-AMP 76 can be in response to the phasecontrol signals HS_PH for the current sense system 100 being configuredas the high-side current sense system 68 or in response to the signalsLS_PH for the current sense system 100 being configured as the low-sidecurrent sense system 70.

The OP-AMP 76 is thus configured to measure the magnitude of therespective one of the phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B),or I_(PH) _(—) _(C) based on the currents I_(REF). For example, for thecurrent sense system 100 being configured as the high-side current sensesystem 68, the switching controller 52 identifies which of the phasecurrents I_(PH) _(—) _(A), I_(PH) _(—) _(B), or I_(PH) _(—) _(C) is thehigh-side sourcing phase current (i.e., the CAP phase current) that isto be measured. The switching controller 52 thus provides the phasecontrol signals HS_PH to the sets of phase switches 108, 110, and 112 toswitch the currents I_(REF) from the respective one of the sets of senseFETs 102, 104, and 106 corresponding to the high-side sourcing phasecurrent to the OP-AMP 76 for the OP-AMP 76 to measure the magnitude ofthe high-side sourcing phase current. Similarly, for the current sensesystem 100 being configured as the low-side current sense system 56, theswitching controller 52 identifies which of the phase currents I_(PH)_(—) _(A), I_(PH) _(—) _(B), or I_(PH) _(—) _(C) is the low-side sinkingphase current (i.e., the GROUND phase current) that is to be measured.The switching controller 52 thus provides the signals LS_PH to the setsof phase switches 108, 110, and 112 to switch the currents I_(REF) fromthe respective one of the sets of sense FETs 102, 104, and 106corresponding to the low-side sinking phase current to the OP-AMP 76 forthe OP-AMP 76 to measure the magnitude of the low-side sourcing phasecurrent.

The OP-AMP 76 thus generates a sense voltage V_(SNS) in response to thecurrents I_(REF). The voltage V_(SNS) can have a magnitude that isproportional to the magnitude of the measured one of the phase currentsI_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C). As an example,the OP-AMP 76 can be configured to conduct approximately equal biascurrents through respective current paths of the OP-AMP 76, such thatthe bias currents set a magnitude of the sense voltage V_(SNS) to beproportional to the respective one of the phase currents I_(PH) _(—)_(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C). For example, the OP-AMP 76can include a cascode amplifier that is controlled by one or both of theconducted bias currents. Accordingly, because the sense voltage V_(SNS)generated by the OP-AMP 76 has a magnitude proportional to the magnitudeof the high-side sourcing phase current or the low-side sinking phasecurrent, the OP-AMP 76 is thus configured to measure the magnitude ofthe high-side sourcing phase current or the low-side sinking phasecurrent.

It is to be understood that the current sense system 100 in the exampleof FIG. 3, as well as the switching system 54, are demonstratedsimplistically. As such, the signal interaction and interconnectionbetween the current sense system 100 and the switching system 54 arelikewise demonstrated simplistically, such that a number of signals havebeen omitted and/or simplified in the example of FIG. 3. Furthermore, itis also to be understood that the current sense system 100 is notlimited to implementing the sets of sense FETs 102, 104, and 106, thesets of phase switches 108, 110, and 112, and/or the OP-AMP 76 tomeasure the respective one or more of the phase currents I_(PH) _(—)_(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C). Accordingly, the currentsense system 100 can be configured in any of a variety of ways.

FIG. 4 illustrates an example of a high-side current-sense system 150 inaccordance with an aspect of the invention. As an example, the high-sidecurrent-sense system 150 in the example of FIG. 4 can correspond to thehigh-side current-sense system 68 in the example of FIG. 2. As such,like reference numbers are used and reference is to be made to theexample of FIGS. 2 in the following description of the example of FIG.4.

Similar to as described above in the example of FIG. 2, the high-sidecurrent-sense system 150 is configured to monitor a magnitude of one ofthe phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), or I_(PH) _(—)_(C) that flows through a respective one of the high-side power FETs,demonstrated in the example of FIG. 4 as high-side power FETs HS_A,HS_B, HS_C. The high-side current-sense system 150 includes respectivesets of sense FETs 152, 154, and 156. In the example of FIG. 4, thesense FETs 152 are demonstrated as a first N-FET N1 and a second N-FETN2, the sense FETs 154 are demonstrated as a third N-FET N3 and a fourthN-FET N4, and the sense FETs 156 are demonstrated as a fifth N-FET N5and a sixth N-FET N6. As an example, each of the N-FETs N1 through N6can have a gate area that is less than the gate area of the high-sidepower FETs HS_A, HS_B, and HS_C.

Each of the first and second N-FETs N1 and N2 are controlled at a gateby the high-side switching signal SW_HS_A that likewise controls thehigh-side power FET HS_A. Similarly, each of the third and fourth N-FETsN3 and N4 are controlled at a gate by the high-side switching signalSW_HS_B that likewise controls the high-side power FET HS_B, and each ofthe fifth and sixth N-FETs N5 and N6 are controlled at a gate by thehigh-side switching signal SW_HS_C that likewise controls the high-sidepower FET HS_C. The first N-FET N1 is coupled at a drain to a phase node158 and is configured to conduct a first reference current I₁ _(—) _(A)that is a first portion of the phase current I_(PH) _(—) _(A) inresponse to the high-side control signal SW_HS_A. The second N-FET N2 iscoupled at a drain to the high-voltage power rail 62 and is configuredto conduct a second reference current I₂ _(—) _(A) from the high-voltagepower rail 62 in response to the high-side control signal SW_HS_A.Similarly, the third N-FET N3 is coupled at a drain to a phase node 160and is configured to conduct a first reference current I₁ _(—) _(B) thatis a first portion of the phase current I_(PH) _(—) _(B) in response tothe high-side control signal SW_HS_B. The fourth N-FET N4 is coupled ata drain to the high-voltage power rail 62 and is configured to conduct asecond reference current I₂ _(—) _(B) from the high-voltage power rail62 in response to the high-side control signal SW_HS_B. The fifth N-FETN5 is coupled at a drain to a phase node 162 and is configured toconduct a first reference current I₁ _(—) _(C) that is a first portionof the phase current I_(PH) _(—) _(C) in response to the high-sidecontrol signal SW_HS_C. The sixth N-FET N6 is coupled at a drain to thehigh-voltage power rail 62 and is configured to conduct a secondreference current I₂ _(—) _(C) from the high-voltage power rail 62 inresponse to the high-side control signal SW_HS_C. The high-side controlsignals SW_HS_A, SW_HS_B, and SW_HS_C can be analog activation signalsthat are generated from the respective high-side drivers in theswitching control circuit 52 as demonstrated in the example of FIG. 2,and can thus constitute one of the switching signals SW_A, SW_B, andSW_C.

The first and second reference currents I₁ _(—) _(A) and I₂ _(—) _(A),as well as a third reference current I₃ _(—) _(A) that is conducted fromthe phase node 158, are provided to a set of phase switches 164. Thephase switches 164 are controlled by a set of phase control signalsHS_PH_A. Similarly, the first and second reference currents I₁ _(—) _(B)and I₂ _(—) _(B), as well as a third reference current I₃ _(—) _(B) thatis conducted from the phase node 160, are provided to a set of phaseswitches 166 controlled by a set of phase control signals HS_PH_B.Furthermore, the first and second reference currents I₁ _(—) _(C) and I₂_(—) _(C), as well as a third reference current I₃ _(—) _(C) that isconducted from the phase node 162, are provided to a set of phaseswitches 168 controlled by a set of phase control signals HS_PH_C. Thephase control signals HS_PH_A, HS_PH_B, and HD₁₃ PH_C can collectivelycorrespond to the phase control signals HS_PH generated by the switchingcontroller 52 in the example of FIG. 2.

It is to be understood that, based on the flow of the first and thirdreference currents I₁ _(—) _(A) and 13 A from the phase node 158, themagnitude of the current flow through the high-side power FET HS_A canbe greater than the magnitude of the output current I_(PH) _(—) _(A)flowing from the phase node 158 to the load (not shown). However, themagnitude of the first and third reference currents I₁ _(—) _(A) and I₃_(—) _(A) can be significantly less than the magnitude of the outputcurrent I_(PH) _(—) _(A), such that the difference in magnitudes betweenthe current flow through the high-side power FET HS_A and the outputcurrent I_(PH) _(—) _(A) can be substantially negligible. It is also tobe understood that the difference in magnitudes between the current flowthrough the high-side power FET HS_B and the output current I_(PH) _(—)_(B), as well as the current flow through the high-side power FET HS_Cand the output current I_(PH) _(—) _(C), can likewise be substantiallynegligible.

The phase control signals HS_PH_A, HS_PH_B, and HS_PH_C are thusprovided by the switching controller 52 to couple a respective one ofthe sets of reference currents I₁ _(—) _(A), I₂ _(—) _(A), and I₃ _(—)_(A); I₁ _(—) _(B), I₂ _(—) _(B), and I₃ _(B); and I₁ _(—) _(C), I₂ _(—)_(C), and I₃ _(—) _(C) to an OP-AMP 170. Therefore, the phase controlsignal HS_PH_A couples the reference currents I₁ _(—) _(A), I₂ _(—)_(A), and I₃ _(—) _(A) to the OP-AMP 170 as the currents I_(REF) via thefirst set of phase switches 164. The phase control signals HS_PH_B andHS_PH_C thus disable the second and third sets of phase switches 166 and168, respectively. Accordingly, the OP-AMP 170 can generate a high-sidesense voltage V_(SNS) _(—) _(HS) that has a magnitude that isproportional to the magnitude of the phase current I_(PH) _(—) _(A).Similarly, the reference currents I₁ _(—) _(B), I₂ _(—) _(B), and I₃_(—) _(B) or the reference currents I₁ _(—) _(C), I₂ _(—) _(C), and I₃_(—) _(C) could instead be coupled to the OP-AMP 170 upon the switchingcontroller 52 identifying that the phase current I_(PH) _(—) _(B) orI_(PH) _(—) _(C), respectively, is the CAP phase current, thus disablingthe other two sets of the phase switches 164, 166, and 168.

In addition to the coupling of the respective reference currents I_(REF)to the OP-AMP 170, the sets of phase switches 164, 166, and 168 can alsobe configured to split the respective sets of reference currents I₁ _(—)_(A), I₂ _(—) _(A), and I₃ _(—) _(A); I₁ _(—) _(B), I₂ _(—) _(B), and I₃_(—) _(B); and I₁ _(—) _(C), I₂ _(—) _(C), and I₃ _(—) _(C) into a sensecurrent, a sense offset current, and a pair of bias currents thatcollectively form the currents I_(REF). As an example, the pair of biascurrents can be approximately equal bias currents that flow throughrespective current paths of the respective one of the sets of phaseswitches 164, 166, and 168 and the OP-AMP 170, such that the biascurrents set a magnitude of the sense current from which the high-sidesense voltage V_(SNS) _(—) _(HS) is generated. Furthermore, therespective one of the sets of phase switches 164, 166, and 168 can beconfigured to pre-bias the electronic components of the OP-AMP 170 priorto the full activation of the respective one of the high-side power FETsHS_A, HS_B, and HS_C. Accordingly, transient effects that can affect themagnitude of the high-side sense voltage V_(SNS) _(—) _(HS) can besubstantially mitigated.

FIG. 5 illustrates an example of a phase switch and OP-AMP arrangement200 in accordance with an aspect of the invention. The phase switch andOP-AMP arrangement 200 includes an OP-AMP 201 that can correspond to theOP-AMP 170 in the examples of FIG. 4. The example of FIG. 5 alsodemonstrates the sets of phase switches 164, 166, and 168. The first setof phase switches 164 is demonstrated as expanded, demonstrating thesignals that are input to it. It is to be understood that the second andthird sets of phase switches 166 and 168 receive a substantially similarset of input signals, with the respective “B” and “C” phase designationsinstead of “A”. Therefore, reference is to be made to the examples ofFIG. 4 in the following description of the example of FIG. 5.

In the example of FIG. 5, upon being provided to the first set of phaseswitches 164, the first reference current I₁ _(—) _(A) is split into afirst bias current I_(B1) and a sense offset current I_(SE) and thesecond reference current I₂ _(—) _(A) is split into a second biascurrent I_(B2) and a sense current I_(SNS). As described in greaterdetail below, the sense offset current I_(SE) can be generated from anexact current source, such that the sense offset current I_(SE) can havea substantially constant magnitude. In addition, the phase controlsignal HS_PH_A and an activation signal HS_ON_A are also provided to thefirst set of phase switches 164. As an example, the phase control signalHS_PH_A and an activation signal HS_ON_A can each be a digital signalthat controls an activation state of a plurality of switches in thefirst set of phase switches 164, as described in greater detail below.As demonstrated in the example of FIG. 5, an OP-AMP input-referredoffset voltage V_(OS) having a minimal magnitude can exist between theinputs of the first set of phase switches 164 that receive the first andsecond bias currents I_(B1) and I_(B2). For example, the magnitude ofthe offset voltage V_(OS) can be based on process and temperaturevariations of the electronic components of the OP-AMP 201.

The OP-AMP 201 includes a current control circuit 202. The currentcontrol circuit 202 includes a first current path 204 that conducts thefirst bias current I_(B1), a second current path 206 that conducts thesecond bias current I_(B2), a third current path 208 that conducts thereference current I₃ _(—) _(A), and a fourth current path 210 thatconducts the sense current I_(SNS). As an example, the first and secondcurrent paths 204 and 206 can be configured substantially the same, suchthat the first and second bias currents I_(B1) and I_(B2) haveapproximately equal magnitudes. Specifically, the first and secondcurrent paths 204 and 206 can be configured as cascode current mirrorsor a cascode amplifier to maintain high sensing linearity over a broadrange of magnitudes of the respective phase current I_(PH) _(—) _(X). Asanother example, to increase the dynamic range of the sense currentI_(SNS) and reduce a systematic offset of the sense current I_(SNS), thethird current path 208 can be configured as a level-shifter that iscontrolled by at least one of the first and second current paths 204 and206. Accordingly, the magnitude of the reference current I₃ _(—) _(A)can be controlled by the first and/or second bias current I_(B1) and/orI_(B2). The output of the level-shifter in the third current path 208can thus control a gate of a pass-MOSFET in the fourth current path 210to generate the magnitude of the sense current I_(SNS) in the fourthcurrent path 210. The high-side sense voltage V_(SNS) _(—) _(HS), whichis output from the current control circuit 202, can be generated fromthe sense current I_(SNS).

The OP-AMP 201 further includes bias current sources 212. The biascurrent sources 212 include a first bias current source 214 thatconducts the first bias current I_(B1), a second bias current source 216that conducts the second bias current I_(B2), and an input bias currentsource 218 that conducts the sense offset current I_(SE). As an example,the first and second bias current sources 214 and 216 can be mirroredfrom a common current source, and the input bias current source 218 canbe an exact current source, such that the sense offset current I_(SE)has a substantially constant magnitude. For example, the sense offsetcurrent I_(SE) can have a magnitude that is selected such that, upon themagnitude of the respective one of the phase currents I_(PH) _(—) _(A),I_(PH) _(—) _(B), and I_(PH) _(—) _(C) being approximately zero, theOP-AMP 201 can be properly biased to maintain sufficient loop gain andspeed under all variations of the offset voltage V_(OS).

As described above in the example of FIG. 4, the sets of phase switches164, 166, and 168 can direct the respective first, second, and thirdreference currents I₁ _(—) _(X), I₂ _(—) _(X), and I₃ _(—) _(X) to theOP-AMP 201 in response to the respective phase control signals HS_PH_A,HS_PH_B, and HS_PH_C. Specifically, upon determining which of the phasecurrents I_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C) is theCAP phase current, the phase control signals HS_PH_A, HS_PH_B, andHS_PH_C corresponding to the other two of the phase currents I_(PH) _(—)_(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C) can be implemented in acommutation cycle to de-couple the current control circuit 202 and/orthe bias current sources 212 from the corresponding sets of sense FETs152, 154, and 156 and the corresponding phase nodes 158, 160, and 162from the OP-AMP 201. In addition, the activation signal HS_ON_Xcorresponding to the CAP phase of the spindle motor phase through whichhigh-side sourcing current flows can be implemented (e.g., de-asserted)prior to full activation of the respective one of the high-side powerFETs HS_X via the high-side switching signal SW_HS_X to couple thecurrent control circuit 202 to the voltage V_(EXT).

As an example, in a PWM cycle of the CAP phase, the activation signalHS_ON_X can be asserted to indicate that the respective one of thehigh-side power FETs HS_X is nearly settled or fully activated in afirst state, thus indicating that the CAP phase current is ready to bemeasured. For example, the activation signal HS_ON_X can be asubstantially delayed version of the respective switching signal SW_HS_Xbased on an amount of time that it takes to activate the respective oneof the high-side power FETs HS_X due to the large gate area of therespective one of the high-side power FETs HS_X. Similarly, theactivation signal HS_ON_X can be de-asserted to indicate that therespective one of the high-side power FETs HS_X will be imminentlydeactivated or fully deactivated in a second state, thus indicating thatthe CAP phase current is not to be measured. Therefore, the electroniccomponents in the current paths 204, 206, 208, and 210, as well as thebias current source 212, can be pre-biased at a substantially settledstate. The pre-biasing of the electronic components in the current paths204, 206, 208, and 210, as well as the bias current source 212 can thussubstantially mitigate transient effects on the sense current I_(SNS),such as in response to switching the high and low-side power FETs HS_Xand LS_X of the CAP phase and can greatly improve sensing speed andaccuracy.

FIG. 6 illustrates an example of a phase switch and OP-AMP circuit 250in accordance with an aspect of the invention. The phase switch andOP-AMP circuit 250 includes an OP-AMP 251 that can correspond to theOP-AMP 201 in the example of FIG. 5, and a set of phase switches 252that can correspond to one of the sets of phase switches 164, 166, or168 in the examples of FIGS. 4 and 5. Therefore, reference is to be madeto the examples of FIGS. 4 and 5 in the following description of theexample of FIG. 6.

The OP-AMP 251 includes the current control circuit 202 and the biascurrent sources 212. The current control circuit 202 includes the firstcurrent path 204 that conducts the first bias current I_(B1) and thesecond current path 206 that conducts the second bias current I_(B2).Each of the first and current paths 204 and 206 include respective PNPbipolar junction transistors (BJTs) Q1 and Q2 in series with respectiveP-MOSFETs P1 and P2. The BJTs Q1 and Q2 are arranged in a cascodedcurrent-mirror configuration via an interposing P-MOSFET P3 having asource that is coupled to the bases of the BJTs Q1 and Q2, a gate thatis coupled to the collector of the BJT Q2, and a drain that is coupledto ground. Similarly, the P-MOSFETs P1 and P2 are arranged in acurrent-mirror configuration based on the coupling of the respectivegates of the P-MOSFETs P1 and P2 and the drain of the P-MOSFET P2 at anode 254. The cascoded current-mirror configuration of the BJTs Q1 andQ2 and P-MOSFETs P1 and P2 is configured to substantially increase theopen-loop gain of the OP-AMP 251, to reduce a current mismatch betweenthe first and second current paths 204 and 206 due to a limited outputimpedance of the BJTs Q1 and Q2, and to maintain substantiallyhigh-sensing linearity over a broad range of magnitudes of therespective phase current I_(PH) _(—) _(X).

In addition, the current control circuit 202 includes the third currentpath 208 that includes a PNP BJT Q3, a diode-configured PNP BJT Q4, anda P-MOSFET P4. The base of the BJT Q3 is coupled to the bases of theBJTs Q1 and Q2, and the gate of the P-MOSFET P4 is coupled to a node 256that is coupled to the drain of the P-MOSFET P1. Therefore, the thirdcurrent path 208 is configured as a level-shifter having a currentmagnitude that is controlled by the first and second current paths 204and 206. The output of the level-shifter of the third current path 208is demonstrated in the example of FIG. 6 as a node 258 that controls agate of a P-MOSFET P5 through which the sense current I_(SNS) flows inthe fourth current path 210. The level-shifter can substantiallyincrease the dynamic range of the sense current I_(SNS) andsubstantially reduce the systematic offset of the sense current I_(SNS).In addition, in the example of FIG. 6, the nodes 254 and 256 areseparated by a series connection of a resistor R_(C1), a capacitor C₁,and a resistor R_(C2), with the resistors R_(C1) and R_(C2) havingapproximately the same resistance magnitude, that are configured tosubstantially increase a sensing speed in response to transients and tostabilize a frequency response associated with the OP-AMP 251.

Additionally, the bias current sources 212 includes a current-mirrornetwork 260 that is configured to generate the first bias current I₁ andthe second bias current I₂. Specifically, the current-mirror network 260includes a current source 262 configured to generate a current I_(SI)that flows through N-MOSFETs N7 and N8 and through a resistor R₂. As anexample, the current source 262 can be generated from an internalvoltage supply. The current-mirror network 260 also includes N-MOSFETsN9 and N10 that are arranged in a current-mirror configuration with theN-MOSFETs N7 and N8, respectively, and a resistor R₃ that is configuredin series with the N-MOSFETs N9 and N10. The N-MOSFETs N9 and N10 andthe resistor R₃ thus constitutes the first bias current source 214 thatconducts the first bias current I_(B1). Similarly, the current-mirrornetwork 260 also includes N-MOSFETs N11 and N12 that are arranged in acurrent-mirror configuration with the N-MOSFETs N7 and N8, respectively,and a resistor R₄ that is configured in series with the N-MOSFETs N11and N12. The N-MOSFETs N11 and N12 and the resistor R₄ thus constitutesthe second bias current source 216 that conducts the second bias currentI_(B2).

The set of phase switches 252 includes a plurality of resistors throughwhich the first, second, and third reference currents I₁ _(—) _(X), I₂_(—) _(X), and I₃ _(—) _(X) flow depending on the state of a pluralityof switches in response to the activation signal HS_ON_X (not shown).Specifically, the set of phase switches 252 includes a first set ofswitches S_(N) _(—) _(OP) and a second set of switches S_(N) _(—) _(PB)that are mutually exclusively controlled by the activation signalHS_ON_X, where N is an integer from 1 to 5 as demonstrated in theexample of FIG. 6. All of the resistors R_(N) _(—) _(PB) and R_(N) _(—)_(OP), as well as the resistors R₂, R₃ and R₄, can be substantially thesame type of the resistors.

Each of the switches S₂ _(—) _(PB), S₃ _(—) _(PB), and S₄ _(—) _(PB)interconnects the high power voltage rail 62 with respective resistorsR₂ _(—) _(PB), R₃ _(—) _(PB), and R₄ _(—) _(PB). The switch S₁ _(—)_(PB) and respective resistor R₁ _(—) _(PB) interconnect the currentsource 218 and the first current path 204 at the emitter of the BJT Q1,and the switch S₅ _(—) _(PB) and respective resistor R₅ _(—) _(PB)interconnect the source of the P-MOSFET P5 and the second current path206 at the emitter of the BJT Q2. Thus, the switches S_(X) _(—) _(PB)are activated by de-asserting the activation signal HS_ON_X forpre-biasing the current control circuit 202, as described in greaterdetail below. Alternatively, the activation signal HS_ON_X is assertedto activate the switches S_(N) _(—) _(OP) to couple the first, second,and third reference currents I₁ _(—) _(X), I₂ _(—) _(X), and I₃ _(—)_(X) to the current control circuit 202 via the respective resistorsR_(N) _(—) _(OP) (demonstrated by the state of the switches S_(N) _(—)_(OP) in the example of FIG. 6). Furthermore, it is to be understoodthat, upon the first, second, and third reference currents I₁ _(—) _(X),I₂ _(—) _(X), and I₃ _(—) _(X) being determined not to be associatedwith the high-side sourcing phase current, the corresponding phasecontrol signal HS_PH_X can open all of the switches S_(N) _(—) _(OP) andS_(N) _(—) _(PB) to decouple the first, second, and third referencecurrents I₁ _(—) _(X), I₂ _(—) _(X), and I₃ _(—) _(X) from the OP-AMP251.

In the example of FIG. 6, the resistors R₂ _(—) _(OP) and R₃ _(—) _(OP)and their respective switches S₂ _(—) _(OP) and S₃ _(—) _(OP), theresistors R₂ _(—) _(PB) and R₃ _(—) _(PB) and their respective switchesS₂ _(—) _(PB) and S₃ _(—) _(PB), the resistors R₁ _(—) _(PB) and R₅ _(—)_(PB) and their respective switches S₁ _(—) _(PB) and S₅ _(—) _(PB), theBJTs Q1 and Q2, the P-MOSFETs P1 and P2, the N-MOSFETs N9 and N11 , theN-MOSFETs N10 and N12, and the resistors R₃ and R₄ can all be matchedcomponents relative to each other, such that the first and second biascurrents I_(B1) and I_(B2) have substantially equal magnitudes. As aresult, the sense current I_(SNS) can have a good power supply rejectionration (PSRR) with respect to the voltage V_(EXT). The current source262 that conducts the current I_(SI), along with the first and secondbias current sources 214 and 216 that conduct the respective currentsI_(B1) and I_(B2), can be such that a voltage drop across the respectiveresistors R₂, R₃, and R₄ remains substantially constant under processand temperature variations. Furthermore, the bias current sources 212include the input bias current source 218 that can be an exact currentsource that conducts the sense offset current I_(SE).

In the example of FIG. 6, just prior to assertion of the activationsignal HS_ON_X, the respective high-side power FET HS_X is about to befully activated, and all of the switches S_(N) _(—) _(OP) are open andall of the switches S_(N) _(—) _(PB) are closed. Therefore, the inputbias current source 218 conducts the sense offset current I_(SE) fromthe voltage V_(EXT) via the resistors R₁ _(—) _(PB) and R₂ _(—) _(PB),and the first and second bias current sources pull the respective firstand second bias currents I_(B1) and I_(B2) from the voltage V_(EXT) viathe respective resistors R₂ _(—) _(PB) and R₃ _(—) _(PB) and therespective first and second current paths 204 and 206. Likewise, thethird reference current I₃ _(—) _(X) flows from the voltage V_(EXT) viathe resistor R₄ _(—) _(PB) and through the third current path 208. Thesense current I_(SNS) flows from the voltage V_(EXT) via the resistorsR₃ _(—) _(PB) and R₅ _(—) _(PB) through the P-MOSFET P5 in the fourthcurrent path 210. Thus, the sense current I_(SNS) can remain at amagnitude that is substantially equal to the magnitude of the senseoffset current I_(SE). As a result, the current control circuit 202 andthe bias current sources 212 are pre-biased at a substantially settledstate. Accordingly, prior to the assertion of the activation signalHS_ON_X, the switching of the respective high-side and low-side powerFETs HS_X and LS_X of the CAP phase has substantially no transienteffect on the magnitude of the sense current I_(SNS).

Upon the activation signal HS_ON_X being asserted, all of the switchesS_(N) _(—) _(OP) are closed and all of the switches S_(N) _(—) _(PB) areopened (i.e., as demonstrated in the example of FIG. 6). Therefore, thesense offset current I_(SE) and the first bias current I_(B1) areconducted from the first reference current I₁ _(—) _(X) (i.e., from thefirst sense FET N1) via the resistors R_(1 OP) and R_(2 OP),respectively. Similarly, the second bias current I_(B2) and the sensecurrent I_(SNS) are conducted from the second reference current I₂ _(—)_(X) (i.e., from the second sense FET N2) via the resistor R₃ _(—) _(OP)and the switch S₅ _(—) _(OP), respectively. Likewise, the thirdreference current I₃ _(—) _(X) is conducted from the respective one ofthe phase nodes 158, 160, and 162 via the resistor R₄ _(—) _(OP), andhas a magnitude that is based on the magnitudes of the first and secondbias currents I_(B1) and I_(B2). The magnitude of the sense currentI_(SNS) is controlled by the voltage magnitude at the node 258.

The OP-AMP 251 thus begins to sense the magnitude of the respectivephase current I_(PH) _(—) _(X). Because the current control circuit 202and the bias current sources 212 are pre-biased at the substantiallysettled state and the respective high-side power FET HS_X issubstantially fully activated, switching transient effects that couldaffect the magnitude of the sense current I_(SNS) are substantiallymitigated. As a result, the sense current I_(SNS) can quickly settle foraccurate sensing of the magnitude of the respective phase current I_(PH)_(—) _(X). The sensing speed and the sensing accuracy are thussubstantially improved, particularly if the PWM frequency becomes toohigh and the PWM duty-cycle becomes too low for the CAP phase.

The OP-AMP 251 continues to track and sense the respective phase currentI_(PH) _(—) _(X) until the activation signal HS_ON_X is de-asserted. Atapproximately the time that the activation signal HS_ON_X becomesde-asserted and the respective high-side power FET HS_X is nearly orfully activated, all of the switches in the set of phase switches 252change state. As a result, the respective high-side power FET HS_N_X andthe sense FETs N1 and N2 are all de-coupled from the OP-AMP 251.Therefore, transient effects on the sense current I_(SNS), such as inresponse to deactivation of the respective high power FETs HS_X, aresubstantially mitigated. While the activation signal HS_ON_X remainsde-asserted, the sense current I_(SNS) is held at approximately the sameamplitude as the sense offset current I_(SE), assuming no variationbetween the associated electronic components. As a result, the currentcontrol circuit 202 and the bias current sources 212 are pre-biased at afavorable settled state to await the next sense request via the nextassertion of the activation signal HS_ON_X.

As described above, the current control circuit 202 includes the fourthcurrent path 210 through which the sense current I_(SNS) flows.Specifically, the sense current I_(SNS) flows through the P-MOSFET P5and a resistor R_(LIM) to a common voltage V_(COM) via a parallelconnection of a resistor R_(F), a capacitor C_(F), and a switch S_(F).As an example, the common voltage V_(COM) can be a negative rail voltagehaving a magnitude that is selected based on an input dynamic range ofthe ADC 78 in the example of FIG. 2. As another example, the commonvoltage V_(COM) can be ground, or can be greater than ground. The switchScan be controlled by the activation signal HS_ON_X or can besubstantially synchronized with the switches S_(X) _(—) _(PB). As anexample, the switch S_(F) can be opened during sensing of the respectivephase current I_(PH) _(—) _(X), such as when the activation signalHS_ON_X is asserted or when the switches S_(X) _(—) _(PB) are opened.The switch S_(F) can be closed when the activation signal HS_ON_X isde-asserted or when the switches S_(X) _(—) _(PB) are closed. As aresult, the resistor R_(F), the capacitor C_(F), and the switch S_(F)are configured to mitigate switching transients and/or otherhigh-frequency noise associated with the sense current I_(SENSE).

The sense current I_(SNS) generates a sense voltage V_(SNS) _(—) _(HS)at a sensing node 264. The resistor R_(LIM) is implemented to limit themagnitude of the sense current I_(SNS), and to thus limit the sensevoltage V_(SNS) _(—) _(HS) at the sensing node 264 based on the voltagedrop across the resistor R_(LIM). In addition, the OP-AMP 251 alsoincludes a voltage clamp 266 that is coupled to the sensing node 264.The voltage clamp 266 is configured to clamp the magnitude of the sensevoltage V_(SNS) _(—) _(HS), such as by shunting excess current toground. As such, the magnitude of the sense voltage V_(SNS) _(—) _(HS)does not exceed the magnitude of a voltage V_(DD). As an example, thevoltage V_(DD) can be an internally provided analog voltage supply forthe ADC 78 that is generated at a magnitude that is less than theexternal voltage V_(EXT). As a result, the ADC 78 can implement smaller,low-voltage electronic devices to conserve IC layout area.

Based on the above described operation of the OP-AMP 251, the magnitudeof the sense current I_(SNS) during sensing of the respective phasecurrent I_(PH) _(—) _(X) can be described by the following expression:

$\begin{matrix}{I_{SNS} = {\left( \frac{I_{PH\_ X}}{M_{PH\_ X}} \right) + I_{OS\_ X} + I_{SE}}} & {{Equation}\mspace{14mu} 1}\end{matrix}$

Where:M_(PH) _(—) _(X) is a proportionality constant of the sizemirroring ratio of the high-side power FET HS_X relative to therespective sense FETs N1 through N6; and

-   -   I_(OS) _(—) _(X) is a sense offset current related to the        respective high-side phase.        As demonstrated by Equation 1, a linear relationship exists        between the magnitude of the sense current I_(SNS) and the phase        current I_(PH) _(—) _(X). To achieve the linear relationship, as        demonstrated in Equation 1, the high-side power FET HS_X and the        respective N-FETs N1 through N6 can be operating well within the        triode/linear region. Based on Equation 1, the sense voltage        V_(SNS) _(—) _(HS) can thus be expressed as follows:

$\begin{matrix}{V_{SNS\_ HS} = {{I_{SNS}*R_{F}} = {\left( {\left( \frac{I_{PH\_ X}}{M_{PH\_ X}} \right) + I_{OS\_ X} + I_{SE}} \right)*R_{F}}}} & {{Equation}\mspace{14mu} 2}\end{matrix}$

As a result, the sense voltage V_(SNS) _(—) _(HS) has a magnitude thatis proportional to the sense current I_(SNS), and thus to the respectivephase current I_(PH) _(—) _(X).

As described above, the first and second bias currents I_(B1) and I_(B2)have substantially equal magnitudes based on substantially matchedelectronic components in each of the set of phase switches 252, thecurrent control circuit 202, and the bias current sources 212. Suchmatching can improve PSRR of the sense current I_(SNS) with respect tothe voltage V_(EXT). In addition, the source degeneration structure ofeach of the bias current sources 212 can improve matching of the biascurrents I_(B1) and I_(B2), thus mitigating the magnitude of aninput-referred offset voltage V_(OS) of the set of phase switches 252and the OP-AMP 251, as well as possible noise contributions of theN-MOSFETs N10 and N12. However, temperature and process variations inthe electronic components of the set of phase switches 252, the currentcontrol circuit 202, and the bias current sources 212 can result in thegeneration of an offset voltage V_(OS) between the inputs of the set ofphase switches 252 and the OP-AMP 251 that receive the first and secondbias currents I_(B1) and I_(B2). The sources of the offset voltageV_(OS) can be quantified based on a number of expressions.

A first contribution V_(OS1) to the offset voltage V_(OS) can resultfrom a mismatch in physical parameters between the N-MOSFETs N10 andN12, as described by the following expression:

$\begin{matrix}{V_{{OS}\; 1} = {\left( \frac{A_{\beta}}{\sqrt{WL}} \right)_{{N\; 10},{N\; 12}}*\frac{1}{1 + \frac{I_{SI}*R_{b}}{\left( \frac{V_{GS} - {Vth}}{2} \right)}}*\left( {V_{T} + {I_{SI}*R_{IN}}} \right)}} & {{Equation}\mspace{14mu} 3}\end{matrix}$

Where: A_(β) is a percentage mismatch parameter between the physicalparameters of the N-MOSFETs N10 and N12;

-   -   WL is a theoretical area of the N-MOSFETs N10 and N12;    -   R_(b) is an average resistance value of the resistors R₂ and R₃;    -   V_(GS) is a gate-source voltage of the N-MOSFETs N10 and N12;    -   Vth is a threshold voltage of the N-MOSFETs N10 and N12;    -   V_(T) is equal to k*T/q; and    -   R_(IN) is an average resistance value of the resistors R₂ _(—)        _(OP) and R₃ _(—) _(OP) in series with the switches S₂ _(—)        _(OP) and S₃ _(—) _(OP), respectively.        A second contribution V_(OS2) to the offset voltage V_(OS) can        result from a mismatch in threshold voltage between the        N-MOSFETs N10 and N12, as described by the following expression:

$\begin{matrix}{V_{{OS}\; 2} = {\left( \frac{A_{Vth}}{\sqrt{WL}} \right)_{{N\; 10},{N\; 12}}*\frac{1}{\left( \frac{V_{GS} - {Vth}}{2} \right) + {I_{SI}*R_{b}}}*\left( {V_{T} + {I_{SI}*R_{IN}}} \right)}} & {{Equation}\mspace{14mu} 4}\end{matrix}$

Where:A_(Vth) is a voltage mismatch parameter between the thresholdvoltages of the N-MOSFETs N10 and N12.A third contribution V_(OS3) to the offset voltage V_(OS) can resultfrom a mismatch in resistance magnitudes between the resistors R₂ andR₃, as described by the following expression:

$\begin{matrix}{V_{{OS}\; 3} = {\left( \frac{\Delta \; R_{b}}{R_{b}} \right)*\frac{1}{1 + \frac{I_{SI}*R_{b}}{\left( \frac{V_{GS} - {Vth}}{2} \right)}}*\left( {V_{T} + {I_{SI}*R_{IN}}} \right)}} & {{Equation}\mspace{14mu} 5}\end{matrix}$

Where:ΔR_(b) is a resistance mismatch between the resistors R₂ and R₃.Equations 3 through 5 above thus represent contributions to the offsetvoltage V_(OS) based on the N-MOSFETs N10 and N12 operating in a stronginversion saturation region. A fourth contribution V_(OS4) to the offsetvoltage V_(OS) can result from a mismatch in resistance magnitudes ofthe resistors R₂ _(—) _(OP) and R₃ _(—) _(OP) in series with theswitches S₂ _(—) _(op) and S₃ _(—) _(OP), respectively, as described bythe following expression:

$\begin{matrix}{V_{{OS}\; 4} = {\left( \frac{\Delta \; R_{IN}}{R_{IN}} \right)*I_{SI}*R_{IN}}} & {{Equation}\mspace{14mu} 6}\end{matrix}$

Where:ΔR_(IN) is a resistance mismatch between the resistors R₂ _(—)_(OP) and R₃ _(—) _(OP) in series with the switches S₂ _(—) _(OP) and S₃_(—) _(OP), respectively.A fifth contribution V_(OS5) to the offset voltage V_(OS) can resultfrom a mismatch in area of the BJTs Q1 and Q2, as described by thefollowing expression:

$\begin{matrix}{V_{{OS}\; 5} = {\left( \frac{A_{C}}{AREA} \right)_{{Q\; 1},{Q\; 2}}*V_{T}}} & {{Equation}\mspace{14mu} 7}\end{matrix}$

Where: A_(C) is a percentage mismatch parameter between the collectorcurrents of the BJTs Q1 and Q2; and

-   -   AREA is a theoretical area of the BJTs Q1 and Q2.        Based on Equations 3 through 7 above, a total magnitude of the        offset voltage V_(OS) can be described by the following        expression:

V_(OS)=√{square root over (V_(OS1) ²+V_(OS2) ²+V_(OS3) ²+V_(OS4)²+V_(OS5) ²)}  Equation 8

A non-zero magnitude of the offset voltage V_(OS) can thus contribute tooffset associated with the sense current I_(SNS).

The offset voltage V_(OS) can be obtained by design optimization ofthese offset contributions based on Equations 3 through 8 above. As aresult, offset and gain can be digitally calibrated for each phase ofthe spindle motor. Specifically, referring back to the example of FIG.2, the ADC 78 samples and converts the sense voltage V_(SNS) _(—) _(HS)across the resistor R_(F). As an example, a full conversion voltagescale V_(ADC) _(—) _(FS) of the ADC 78 can be proportional to theresistance magnitude of the resistor R_(F), such that the conversiondigital output code of the ADC 78 is independent on any processvariations of the resistor R_(F). Assuming the full conversion voltagescale V_(ADC) _(—) _(FS) can be expressed as I_(ADC) _(—)_(REF)*R_(ADC), where R_(ADC) approximately matches the resistor R_(F)with a ratio of K and the current I_(ADC) _(—) _(REF) is the exactreference current, the sampled sense voltage V_(SNS) _(—) _(HS) can beexpressed as a digital value D_(ADC) _(—) _(OUT). Specifically,referring back to Equation 2, the digital value D_(ADC) _(—) _(OUT) canbe expressed as follows:

$\begin{matrix}\begin{matrix}{D_{ADC\_ OUT} = \frac{V_{SNS\_ HS}}{V_{ADC\_ FS}}} \\{= \frac{I_{SNS}*R_{F}}{I_{ADC\_ REF}*R_{ADC}}} \\{= \frac{\left( {\left( \frac{I_{PH\_ X}}{M_{PH\_ X}} \right) + I_{OS\_ X} + I_{SE}} \right)}{I_{ADC\_ REF}*K}}\end{matrix} & {{Equation}\mspace{14mu} 9}\end{matrix}$

Equation 9 also demonstrates the digital value for the magnitude of therespective one of the phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B),and I_(PH) _(—) _(C) that is the high-side sourcing phase current. Basedon Equation 9, a linear relationship between the respective phasecurrent I_(PH) _(—) _(X) and the respective digital value D_(ADC) _(—)_(OUT) can be described by the following expressions:

I _(PH) _(—) _(X)=GAIN_(PH) _(—) _(X) *D _(ADC) _(—) _(OUT)−OFFSET_(PH)_(—) _(X)   Equation 10

OFFSET_(PH) _(—) _(X) =M _(PH) _(—) _(X)*(I _(OS) _(—) _(X) +I _(SE))  Equation 11

GAIN_(PH) _(—) _(X) =K*M _(PH) _(—) _(X) *I _(ADC) _(—) _(REF)  Equation 12

The offset and gain associated with each high-side phase can vary withprocess and temperature variations. In order to accurately sense therespective one of the phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B),and I_(PH) _(—) _(C), the offset and gain calibration can be performedfor each high-side phase of the spindle motor. For example, in theexample of FIG. 2, the respective known high-side sourcing phasecurrents I_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C) can beprovided to the spindle motor power regulator system 50, such as duringoperation of the spindle motor or externally through the respectivehigh-side power transistors 56, 58 and 60. The high-side current sensesystem 68 and the ADC 78 can be configured to measure the magnitude ofthe respective known phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B),and I_(PH) _(—) _(C) and to generate the respective digital value,respectively. An optimization algorithm or routine can be employed toperform the calibration and extract and store conversion gain and/oroffset information for each phase. As an example, the processor 80 canstore the respective high-side gains GAIN_(PH A), GAIN_(PH B), andGAIN_(PH C) and the respective high-side offsets OFFSET_(PH) _(—) _(A),OFFSET_(PH) _(—) _(B), and OFFSET_(PH) _(—) _(C) in the digital format.The processor 80 can thus implement the stored high-side gain and/oroffset information to subsequently calculate the respective high-sidesourcing phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH)_(—) _(C) by implementing Equation 10.

It is to be understood that the phase switch and OP-AMP circuit 250 isnot intended to be limited to the example of FIG. 6. As an example,additional circuit configurations for each of the set of phase switches252, current control circuit 202, and the bias current sources 212 areconceivable for the phase switch and OP-AMP circuit 250. Accordingly,the phase switch and OP-AMP circuit 250 can be configured in any of avariety of ways.

FIG. 7 illustrates an example of a low-side current-sense system 300 inaccordance with an aspect of the invention. As an example, the low-sidecurrent-sense system 300 in the example of FIG. 7 can correspond to thelow-side current-sense system 70 in the example of FIG. 2. As such, likereference numbers are used and reference is to be made to the example ofFIG. 2 in the following description of the example of FIG. 7.

Similar to as described above in the example of FIG. 2, the low-sidecurrent-sense system 300 is configured to monitor a magnitude of one ofthe phase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), or I_(PH) _(—)_(C) that flows through a respective one of the low-side power FETs,demonstrated in the example of FIG. 7 as low-side power FETs LS_A, LS_B,LS_C. The low-side current-sense system 300 includes respective sets ofsense FETs 302, 304, and 306. In the example of FIG. 7, the sense FETs302 are demonstrated as a first N-FET N13 and a second N-FET N14, thesense FETs 304 are demonstrated as a third N-FET N15 and a fourth N-FETN16, and the sense FETs 306 are demonstrated as a fifth N-FET N17 and asixth N-FET N18. As an example, each of the N-FETs N13 through N18 canhave a gate area that is less than the gate area of the low-side powerFETs LS_A, LS_B, and LS_C.

Each of the first and second N-FETs N13 and N14 are controlled at a gateby the low-side switching signal SW_LS_A that likewise controls thelow-side power FET LS_A. Similarly, each of the third and fourth N-FETsN15 and N16 are controlled at a gate by the low-side switching signalSW_LS_B that likewise controls the low-side power FET LS_B, and each ofthe fifth and sixth N-FETs N17 and N18 are controlled at a gate by thelow-side switching signal SW_LS_C that likewise controls the low-sidepower FET LS_C. The first N-FET N13 is coupled at a source to the phasenode 158 and is configured to conduct a first reference current I₁ _(—)_(A) that is a first portion of the phase current I_(PH) _(—) _(A) inresponse to the low-side control signal SW_LS_A. The second N-FET N14 iscoupled at a source to the low-voltage power rail 64 and is configuredto conduct a second reference current I₂ _(—) _(A) to the low-voltagepower rail 64 in response to the low-side control signal SW_LS_A.Similarly, the third N-FET N15 is coupled at a source to the phase node160 and is configured to conduct a first reference current I₁ _(—) _(B)that is a first portion of the phase current I_(PH) _(—) _(B) inresponse to the low-side control signal SW_LS_B. The fourth N-FET N16 iscoupled at a source to the low-voltage power rail 64 and is configuredto conduct a second reference current I₂ _(—) _(B) from the low-voltagepower rail 64 in response to the low-side control signal SW_LS_B. Thefifth N-FET N17 is coupled at a source to the phase node 162 and isconfigured to conduct a first reference current I₁ _(—) _(C) that is afirst portion of the phase current I_(PH) _(—) _(C) in response to thelow-side control signal SW_LS_C. The sixth N-FET N18 is coupled at adrain to the low-voltage power rail 64 and is configured to conduct asecond reference current I₂ _(—) _(C) from the low-voltage power rail 64in response to the low-side control signal SW_LS_C.

It is to be understood that the low-side control signals SW_LS_A,SW_LS_B and SW_LS_C can be analog activation signals that are generatedfrom the respective low-side drivers in the switching control circuit 52as demonstrated in the example of FIG. 2, and can thus constitute one ofthe switching signals SW_A, SW_B and SW_C. In addition, the phase nodes158, 160 and 162 in the example of FIG. 7 can be the same nodescorresponding, respectively, to the phase nodes 158, 160 and 162 in theexample of FIG. 4. Furthermore, the drains of the N-FETs N13, N15, andN17 in the example of FIG. 7 can be connected respectively with thesources of the N-FETs N1, N3, and N5 in the example of FIG. 4.

The first and second reference currents I₁ _(—) _(A) and I₂ _(—) _(A),as well as third reference current I₃ _(—) _(A) that is conducted fromthe phase node 158, are provided to a set of phase switches 314. Thephase switches 314 are controlled by a set of phase control signalsLS_PH_A. Similarly, the first and second reference currents I₁ _(—) _(B)and I₂ _(—) _(B), as well as third reference current I₃ _(—) _(B) thatis conducted from the phase node 160, are provided to a set of phaseswitches 316 controlled by a set of phase control signals LS_PH_B.Furthermore, the first and second reference currents I₁ _(—) _(C) and I₂_(—) _(C), as well as third reference current I₃ _(—) _(C) that isconducted from the phase node 162, are provided to a set of phaseswitches 318 controlled by a set of phase control signals LS_PH_C. Thephase control signals LS_PH_A, LS_PH_B, and LS_PH_C can collectivelycorrespond to the phase control signals LS_PH generated by the switchingcontroller 52 in the example of FIG. 2.

It is to be understood that, based on the flow of the first and thirdreference currents I₁ _(—) _(A) and I₃ _(—) _(A) into the phase node158, the magnitude of the current flow through the low-side power FETLS_A can be greater than the magnitude of the output current I_(PH) _(—)_(A) flowing into the phase node 158 from the load (not shown). However,the magnitude of the first and third reference currents I₁ _(—) _(A) andI₃ _(—) _(A) can be significantly less than the magnitude of the outputcurrent I_(PH) _(—) _(A), such that the difference in magnitudes betweenthe current flow through the low-side power FET LS_A and the outputcurrent I_(PH) _(—) _(A) can be substantially negligible. It is also tobe understood that the difference in magnitudes between the current flowthrough the low-side power FET LS_B and the output current I_(PH) _(—)_(B), as well as the current flow through the low-side power FET LS_Cand the output current I_(PH) _(—) _(C), can likewise be substantiallynegligible.

The phase control signals LS_PH_A, LS_PH_B, and LS_PH_C are thusprovided by the switching controller 52 to switch a respective one ofthe sets of reference currents I₁ _(—) _(A), I₂ _(—) _(A), and I₃ _(—)_(A); I₁ _(—) _(B), I₂ _(—) _(B), and I₃ _(—) _(B); and I₁ _(—) _(C), I₂_(—) _(C), and I₃ _(—) _(C) from an OP-AMP 320. Therefore, the phasecontrol signal LS_PH_A switches currents I_(REF) generated from theOP-AMP 320 as the reference currents I₁ _(—) _(A), I₂ _(—) _(A), and I₃_(—) _(A) via the first set of phase switches 314. The phase controlsignals LS_PH_B and LS_PH_C thus disable the second and third sets ofphase switches 316 and 318, respectively. Accordingly, the OP-AMP 320can generate a low-side sense voltage V_(SNS) _(—) _(LS) that has amagnitude that is proportional to the magnitude of the phase currentI_(PH) _(—) _(A). Similarly, the reference currents I₁ _(—) _(B), I₂_(—) _(B), and I₃ _(—) _(B) or the reference currents I₁ _(—) _(C), I₂_(—) _(C), and U₃ _(—) _(C) could instead be switched from the OP-AMP320 upon the switching controller 52 identifying that the phase currentI_(PH) _(—) _(B) or I_(PH) _(—) _(C), respectively, is the low-sidesinking phase current, thus disabling the other two sets of the phaseswitches 314, 316, and 318.

In addition to the coupling of the respective reference currents I_(REF)from the OP-AMP 320, the sets of phase switches 314, 316, and 318 canalso be configured to split the respective sets of reference currents I₁_(—) _(A), I₂ _(—) _(A), and I₃ _(—) _(A); I₁ _(—) _(B), I₂ _(—) _(B),and I₃ _(—) _(B); and I₁ _(—) _(C), I₂ _(—) _(C), and I₃ _(—) _(C) intoa sense current, a sense offset current, and a pair of bias currentsthat collectively form the currents I_(REF), similar to as describedabove regarding the high-side current sense system 150. As an example,the pair of bias currents can be approximately equal bias currents thatflow through respective current paths of the respective one of the setsof phase switches 314, 316, and 318 and the OP-AMP 320, such that thebias currents set a magnitude of the sense current from which thelow-side sense voltage V_(SNS) _(—) _(LS) is generated. Furthermore, therespective one of the sets of phase switches 314, 316, and 318 can beconfigured to pre-bias the electronic components of the OP-AMP 320 priorto the full activation of the respective one of the low-side power FETsLS_A, LS_B, and LS_C. Accordingly, transient effects that can affect themagnitude of the low-side sense voltage V_(SNS) _(—) _(LS) can besubstantially mitigated.

Based on the above description of the low-side current-sense circuit300, it is demonstrated that the low-side current-sense circuit 300operates substantially similar to the high-side current-sense circuit150. As an example, the OP-AMP 320 in the example of FIG. 7 can beconfigured as a substantially inverted version of the OP-AMP 251 in theexample of FIG. 6, such as to include a reversed current-flow directionof the first and second reference currents I₁ _(—) _(X) and I₂ _(—)_(X), and thus also of the first and second bias currents I_(B1) andI_(B2). For example, the OP-AMP 320 can include a current controlcircuit, similar to the current control circuit 202, that includes NPNBJTs and N-MOSFETs in the current paths for the first and second biascurrents I_(B1) and I_(B2) and the third reference current I₃ _(—) _(X).Similarly, the OP-AMP 320 can include bias current sources that conductthe currents I_(SE), I_(SI), I_(B1), and I_(B2) from the voltage V_(INT)or the voltage V_(EXT) at the positive voltage rail 62, such as viaP-MOSFETs in the case of the currents I_(S1), I_(B1), and I_(B2).

Furthermore, it is to be understood that the direction of the flow ofthe low-side sense current can be from an internal voltage V_(COM) tothe respective one of sense FETs N14, N16, and N18, or can be changed byadding one or more current mirrors to the OP-AMP 320. Accordingly, thelow-side current-sense system 300 can be configured in any of a varietyof ways. It is also to be understood that, in order to accurately sensethe respective one of the phase currents I_(PH) _(—) _(A), I_(PH) _(—)_(B), and I_(PH) _(—) _(C), the spindle motor power regulator system 50in the example of FIG. 2 can be configured to perform the offset andgain calibration for each low-side phase of the spindle motor. Theprocessor 80 can thus implement the stored low-side gain and/or offsetinformation to subsequently calculate the respective low-side sourcingphase currents I_(PH) _(—) _(A), I_(PH) _(—) _(B), and I_(PH) _(—) _(C)by implementing Equation 10.

In view of the foregoing structural and functional features describedabove, certain methods will be better appreciated with reference to FIG.8. It is to be understood and appreciated that the illustrated actions,in other embodiments, may occur in different orders and/or concurrentlywith other actions. Moreover, not all illustrated features may berequired to implement a method.

FIG. 8 illustrates an example of a method 350 for determining individualphase currents of a disk-drive spindle motor in accordance with anaspect of the invention. At 352, a plurality of switching signals thatcontrol at least one power transistor are generated for each of theplurality of phases of the disk-drive spindle motor. The switchingsignals can be provided from a switching controller, and can be providedto a set of power transistors, such as a high-side and low-side powerFET for each phase of the spindle motor. At 354, it is identified whichof at least one of the plurality of phases through which the respectiveindividual phase current is to be measured based on the plurality ofswitching signals. The measurement can be a CAP phase current, which canbe a current that is substantially constantly sourced to one of thephases of the spindle motor in a commutation cycle, and of a GROUNDphase current, which can be a current that is substantially constantlysunk from a second one of the phases of the spindle motor to alow-voltage power rail. The identification can be based on the switchingsignal having the greatest PWM duty-cycle in each PWM period of thecommutation cycle in the case of the CAP phase current (i.e., relativeto a SLOPE phase current) and the switching signal having no PWMduty-cycle in the case of the low-side sinking phase current.

At 356, a plurality of reference currents corresponding to therespective individual phase current are switched to a respective currentsense system. The respective current sense system can include ahigh-side current sense system to measure the high-side sourcing phasecurrent and a low-side current sense system to measure the low-sidesinking phase current. The reference currents can be generated from arespective plurality of sense FETs arranged with respect to therespective one of the high-side or low-side FETs through which therespective phase current flows. At 358, the magnitude of the respectiveindividual phase current of the at least one of the plurality of phasesis measured based on the plurality of reference currents. A sensevoltage having a magnitude that is proportional to the magnitude of therespective phase current can be generated from an OP-AMP in response tothe reference currents.

At 360, a magnitude of one or more remaining phase currents iscalculated based on the magnitude of the respective individual phasecurrent. The phase voltage(s) can be provided to an ADC that convertsthe sense voltage to a digital value. The digital value of the high-sidesourcing phase current and the low-side sinking phase current can beused to calculate the magnitude of the third phase current of thespindle motor. The digital values can also be implemented in acalibration routine for the subsequent measurement of the CAP phasecurrents. For example, the sourcing current can be measured individuallythrough each of the phases of the spindle motor, and offset and/or gaininformation can be ascertained from the digital values. The offsetand/or gain information can then be implemented in subsequentmeasurements of the CAP phase current through each of the phases of thespindle motor. Therefore, the magnitude of all three phase currents ofthe spindle motor can be identified by a respective processor, such thatcommutation speed information associated with the spindle motor can beimplemented to adjust and/or control the rotation speed of the spindlemotor.

What have been described above are examples of the invention. It is, ofcourse, not possible to describe every conceivable combination ofcomponents or methodologies for purposes of describing the invention,but one of ordinary skill in the art will recognize that many furthercombinations and permutations of the invention are possible.Accordingly, the invention is intended to embrace all such alterations,modifications, and variations that fall within the scope of thisapplication, including the appended claims.

1. A disk-drive spindle motor power regulator system comprising: aswitching system comprising at least one power transistor for each of aplurality of phases of a disk-drive spindle motor; a switchingcontroller configured to generate a plurality of switching signalsconfigured to control the at least one power transistor for each of theplurality of phases of the disk-drive spindle motor; a current monitorconfigured to measure a magnitude of an individual phase current throughat least one of the plurality of phases of the disk-drive spindle motor.2. The system of claim 1, wherein the current monitor is configured tomeasure a first phase current that is substantially constantly sourcedto a respective first one of the plurality of phases of the disk-drivespindle motor in a commutation cycle and to measure a magnitude of asecond phase current that is substantially constantly sunk from arespective second one of the plurality of phases of the disk-drivespindle motor to a low voltage power rail in the commutation cycle. 3.The system of claim 1, wherein the current monitor comprises at leastone current sense system configured to measure the magnitude of theindividual phase current through the respective at least one of theplurality of phases of the disk-drive spindle motor.
 4. The system ofclaim 3, wherein each of the at least one current sense systemcomprises: a first sense transistor configured to conduct a firstreference current one of to and from a phase node associated with therespective one of the plurality of phases of the disk-drive spindlemotor; a second sense transistor configured to conduct a secondreference current one of to and from a power rail; and an operationalamplifier (OP-AMP) configured to receive the first reference current,the second reference current, and a third reference current that flowsone of to and from the phase node associated with the respective one ofthe plurality of phases of the disk-drive spindle motor and to generatea sense voltage that is substantially proportional to the individualphase current.
 5. The system of claim 4, wherein the first sensetransistor and the second sense transistor comprise a first of aplurality of sense transistor pairs that each correspond to a respectiveone of the plurality of phases of the spindle motor, and wherein theOP-AMP comprises a switching control circuit that is configured toselectively couple the OP-AMP with one of the plurality of sensetransistor pairs for the OP-AMP to measure the corresponding individualphase current.
 6. The system of claim 5, wherein the switching systemcouples the OP-AMP to the respective one of the plurality of sensetransistor pairs in response to a set of phase control signals for theOP-AMP to measure one of a magnitude of a first phase current that issubstantially constantly sourced to a respective first one of theplurality of phases of the disk-drive spindle motor in a commutationcycle and a magnitude of a second phase current that is substantiallyconstantly sunk from a respective second one of the plurality of phasesof the disk-drive spindle motor to a low voltage power rail in thecommutation cycle.
 7. The system of claim 3, wherein the plurality ofphases comprises three phases, the at least one current sense systemcomprising: a high-side current sense system configured to measure afirst phase current that is substantially constantly sourced to arespective first one of the plurality of phases of the disk-drivespindle motor in a commutation cycle based on a respective first one ofthe plurality of switching signals having a greatest duty-cycle in eachpulse width modulation (PWM) period of the commutation cycle; and alow-side current sense system configured to measure a magnitude of asecond phase current that is substantially constantly sunk from arespective second one of the plurality of phases of the disk-drivespindle motor to a low voltage power rail in the commutation cycle basedon a respective second one of the plurality of switching signals havingno duty-cycle.
 8. The system of claim 7, wherein the high-side currentsense system is further configured to generate a high-side sense voltagethat is proportional to a magnitude of the first phase current andwherein the low-side current sense system is further configured togenerate a low-side sense voltage that is proportional to a magnitude ofthe second phase current, and wherein the current monitor furthercomprises: an analog-to-digital converter (ADC) configured to converteach of the first and second sense voltages to digital valuescorresponding to the magnitudes of the first and second phase currents,respectively; and a processor configured to calculate a magnitude of athird phase current based on the digital values and to generate afeedback control signal corresponding to a commutation speed of thedisk-drive spindle motor.
 9. An integrated circuit comprising thedisk-drive spindle motor power regulator system of claim
 1. 10. A methodfor determining individual phase currents of a disk-drive spindle motor,the method comprising: generating a plurality of switching signals thatcontrol at least one power transistor for each of the plurality ofphases of the disk-drive spindle motor; identifying which of at leastone of the plurality of phases through which the respective individualphase current is to be measured based on the plurality of switchingsignals; switching a plurality of reference currents corresponding tothe respective individual phase current to a respective current sensesystem; measuring the magnitude of the respective individual phasecurrent of the at least one of the plurality of phases based on theplurality of reference currents; and calculating a magnitude of one ormore remaining phase currents based on the magnitude of the respectiveindividual phase current.
 11. The method of claim 10, whereinidentifying which of the at least one of the plurality of phases throughwhich the respective individual phase current is measured comprises:identifying measurement of a first phase current that is substantiallyconstantly sourced to a respective first one of the plurality of phasesof the disk-drive spindle motor in a commutation cycle based on arespective first one of the plurality of switching signals associatedwith the first phase current having a greatest pulse width modulation(PWM) duty-cycle in each PWM period of the commutation cycle; andidentifying a magnitude of a second phase current flowing that issubstantially constantly sunk from a respective second one of theplurality of phases of the disk-drive spindle motor to a low voltagepower rail in the commutation cycle based on a respective second one ofthe plurality of switching signals associated with the second phasecurrent having no PWM duty-cycle; wherein measuring the magnitude of therespective individual phase current comprises measuring the magnitude ofthe first phase current and the second phase current.
 12. The method ofclaim 11, further comprising converting the magnitude of the first phasecurrent and the second phase current to respective digital values, andwherein calculating the magnitude of one or more remaining phasecurrents comprises calculating a magnitude of a third phase currentbased on the digital values.
 13. The method of claim 11, furthercomprising: implementing a calibration routine to calculate at least oneof offset and gain information associated with each of the plurality ofphases of the disk-drive spindle motor; and storing the at least one ofthe offset and gain information to compensate for at least one ofprocess and temperature variations in measuring the magnitude of thefirst phase current.
 14. The method of claim 13, wherein implementingthe calibration routine comprises: measuring a sourcing current througheach of the plurality of phases of the disk-drive spindle motor;generating digital values associated with the measured sourcing currentthrough each of the plurality of phases of the disk-drive spindle motor;and calculating the at least one of the offset and gain informationbased on the digital values.
 15. The method of claim 10, furthercomprising: generating a first reference current one of to and from aphase node associated with the at least one of the plurality of phasesof the disk-drive spindle motor via a first sense transistor; andgenerating a second reference current one of to and from a power railvia a second sense transistor; wherein switching a plurality ofreference currents comprises switching the first and second referencecurrents to an operational amplifier (OP-AMP) configured to generate thesense voltage in response to the first reference current, the secondreference current, and a third reference current that flows one of toand from the phase node associated with the at least one of theplurality of phases of the disk-drive spindle motor.
 16. The method ofclaim 10, wherein switching the plurality of reference currentscorresponding to the respective individual phase current to therespective current sense system comprises: switching a first pluralityof reference currents corresponding to a first phase current flowingfrom a high-voltage power rail through a respective first one of theplurality of phases of the disk-drive spindle motor to a high-sidecurrent sense system; and switching a second plurality of referencecurrents corresponding to a second phase current flowing through arespective second one of the plurality of phases of the disk-drivespindle motor to a low-side current sense system.
 17. A disk-drivespindle motor power regulator system comprising: means for generating aplurality of switching signals associated with each of a first phase, asecond phase, and a third phase, respectively, of the disk-drive spindlemotor; means for generating a first phase current, a second phasecurrent, and a third phase current through the first, second, and thirdphases respectively, of the disk-drive spindle motor in response to theplurality of switching signals; means for measuring a magnitude of twoof the first, second, and third phase currents; and means forcalculating a magnitude of a remaining one of the first, second, andthird phase currents based on the measured magnitude of the two of thefirst, second, and third phase currents.
 18. The system of claim 17,wherein the means for measuring comprises: means for generating a firstsense voltage corresponding to a magnitude of a first one of the first,second, and third phase currents; means for generating a second sensevoltage corresponding to a magnitude of a second one of the first,second, and third phase currents; means for switching a first one of thefirst, second, and third phase currents to the means for generating thefirst sense voltage; and means for switching a second one of the first,second, and third phase currents to the means for generating the secondsense voltage in response to the plurality of switching signals.
 19. Thesystem of claim 18, wherein the means for generating the plurality ofswitching signals comprises means for identifying the first one of thefirst, second, and third phase currents that is substantially constantlysourced to a respective first one of the first, second, and third phasesof the disk-drive spindle motor in a commutation cycle to be measuredand for measuring the second one of the first, second, and third phasecurrents that is substantially constantly sunk from a respective secondone of the plurality of phases of the disk-drive spindle motor to a lowvoltage power rail in the commutation cycle to be measured.
 20. Thesystem of claim 18, further comprising means for converting the firstand second sense voltages to digital values, the means for calculatingbeing configured to calculate the remaining one of the first, second,and third phase currents based on the digital values.